DFPIC1655X Datasheet, PDF (2/7 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

PERIPHERALS
● Two 8 bit I/O ports
○ Four 8-bit corresponding TRIS registers
○ Interrupt feature on PORTB(7:4) change
● Timer 0
○ 8-bit timer/counter
○ Readable and Writable
○ 8-bit software programmable prescaler
○ Internal or external clock select
○ Interrupt generation on timer overflow
○ Edge select for external clock
● Watchdog Timer
○ Configurable Time out period
○ 7-bit software programmable prescaler
○ Dedicated independent Watchdog Clock input
● Interrupt Controller
○ Three individually maskable Interrupt sources
○ External interrupt INT
○ Timer Overflow interrupt
○ Port B[7:4] change interrupt
● DoCD™ debug unit
○ Processor execution control
○ Run
○ Halt
○ Step into instruction
○ Skip instruction
○ Read-write all processor contents
○ Program Counter (PC)
○ Program Memory
○ Data Memory
○ Special Function Registers (SFRs)
○ Hardware Stack and Stack Pointer
○ Hardware execution breakpoints
○ Program Memory
○ Data Memory
○ Special Function Registers (SFRs)
○ Hardware breakpoints activated at a certain
○ Program address (PC)
○ Address by any write into memory
○ Address by any read from memory
○ Address by write into memory a required data
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○ Address by read from memory a required data
○ Three wire communication interface
CONFIGURATION
The following parameters of the DFPIC1655X
core can be easy adjusted to requirements of
dedicated application and technology. Con-
figuration of the core can be prepared by ef-
fortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
• MEMORY Type
•
Number
levels
of
hardware
stack
• Program Memory size
• SLEEP mode
• WATCHDOG Timer
• Timer system
• PORTS A,B
• DoCD^TM Debug Unit
- synchronous
- asynchronous
- 1-16
- default 4
- up 64 kWords
- default 8k
- used
- unused
- used / width
- unused
- used
- unused
- used
- unused
- used
- unused
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted Megafunction or/and
◊ plain text EDIF
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
http://www.DigitalCoreDesign.com
http://www.dcd.pl
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