DFPIC1655X Datasheet, PDF (1/7 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

DFPIC1655X
High Performance Configurable
8-bit RISC Microcontroller
ver 2.02
OVERVIEW
The DFPIC1655X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core, dedi-
cated for operation with fast memory (typi-
cally on-chip). The core has been designed
with a special concern about low power con-
sumption.
The DFPIC1655X is software compatible
with the industry standard PIC16C554 and
PIC16C558. It employs a modified RISC
architecture (2 times faster than original
implementation).
The DFPIC1655X have enhanced core
features, configurable hardware stack, and
multiple internal and external interrupt
sources. The separate instruction and data
buses allow a 14 bit wide instruction word with
the separate 8 -bit wide data. The
DFPIC1655X typically achieve a 2:1 code
compression and a 8:1 speed improvement
over other 8-bit microcontrollers in their class.
The power-down mode SLEEP allow user
to reduce power consumption. User can wake
up the controller from SLEEP through several
external and internal interrupt and reset. An
integrated Watchdog Timer with it's own clock
signal provides protection against software
lock-up.
The DFPIC1655X Microcontroller fits
perfectly in applications ranging from high-
speed automotive and appliance motor control
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to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode and small used area
in programmable devices make this IP perfect
for applications applications with space and
power consumption limitations.
DFPIC1655X is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow
CPU FEATURES
● Software compatible with industry standard
PIC16C55X
● Harvard architecture 2 times faster com-
pared to original implementation
● 35 instructions
● 14 bit wide instruction word
● Up to 512 bytes of internal Data Memory
● Up to 64K bytes of Program Memory
● Configurable hardware stack
● Power saving SLEEP mode
● Fully synthesizable, static synchronous
design with no internal tri-states
● Scan test ready
● Technology independent HDL Source
Code
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