3D3424 Datasheet, PDF (2/6 Pages) Data Delay Devices, Inc. – MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

3D3424
APPLICATION NOTES
THEORY OF OPERATION
The quad 4-bit programmable 3D3424 device
architecture is comprised of four independently
operating delay lines. Each delay line produces
at its output a replica of the signal present at its
input, shifted in time. A single delay line is
comprised of a number of delay cells connected
in series. Delay selection is achieved by routing
one output in each string of cells to its respective
output pin (O1-O4). The delay of each of the four
lines can be controlled independently, via the
serial interface, as described in the next section.
The change in delay from one address setting to
the next is called the increment, or LSB. It is
nominally equal to the device dash number. The
minimum delay, achieved by setting the address
of a line to zero, is called the inherent delay.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
I4
DELAY
LINE
O4
I3
DELAY
LINE
O3
I2
DELAY
LINE
O2
I1
DELAY
LINE
O1
ADDR4
ADDR3
ADDR2
ADDR1 ENABLES
AL
20-BIT LATCH
SI
20-BIT SHIFT REGISTER
SO
SC
Figure 1: Functional block diagram
PROGRAMMED DELAY INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D3424 device. Since the device is a CMOS
design, all unused input pins must be returned to
well defined logic levels (VDD or GND). The
delays are adjusted by first shifting a 20-bit
programming word into the device via the SC and
SI pins, then strobing the AL signal to latch the
values. The bit sequence is shown in Table 2,
and the associated timing diagram is shown in
Figure 2. Each line has associated with it an
enable bit. Setting this bit low will force the
corresponding delay line output to a high
impedance state, while setting it high returns the
line to its normal operation. The device contains
an SO output, which can be used to cascade
multiple devices, as shown in Figure 3.
TABLE 2: BIT SEQUENCE
Bit Delay
Line
1
4
2
3
3
2
4
1
5
1
6
7
8
9
2
10
11
12
13 3
14
15
16
17 4
18
19
20
Function
Output Enable
Output Enable
Output Enable
Output Enable
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
LATCH
(AL)
tCW tCW
CLOCK
(SC)
SERIAL
INPUT
(SI)
tDSC
NEW
BIT 1
SERIAL
OUTPUT
(SO)
OLD
BIT 1
tDHC
NEW
BIT 2
tPCQ
OLD
BIT 2
DELAY
TIMES
PREVIOUS VALUES
tLW
t_CSL
NEW
BIT 20
OLD
BIT 20
tLDX
NEW
BIT 1
tLDV
NEW
VALUES
Figure 2: Serial interface timing diagram
Doc #06020
DATA DELAY DEVICES, INC.
2
6/6/2006
Tel: [phone] Fax: [phone] http://www.datadelay.com