DS80C310_09 Datasheet, PDF (9/22 Pages) Dallas Semiconductor – High-Speed Microcontroller

DS80C310
Table 2. Data Memory Cycle Stretch Values
CKCON.2–CKCON.0
M2 M1 M0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MEMORY
CYCLES
2
3 (default)
4
5
6
7
8
9
RD OR WR STROBE
WIDTH IN CLOCKS
2
4
8
12
16
20
24
28
25MHz STROBE WIDTH
(ns)
80
160
320
480
640
800
960
1120
DUAL DATA POINTER (DPTR)
Data memory block moves can be accelerated using the DS80C310 dual data pointer (DPTR). The
standard 8032 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These
are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is
located at SFR 84h and 85h and is called DPTR1. The DPTR select bit (DPS) chooses the active pointer
and is located at the LSB of the SFR location 86h. No other bits in register 86h have any effect and are set
to 0. The user switches between data pointers by toggling the LSB of register 86h. The increment (INC)
instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected
DPTR for any activity. Therefore, only one instruction is required to switch from a source to a destination
address. Using the DPTR saves code from needing to save source and destination addresses when doing a
block move. Once loaded, the software simply switches between DPTR0 and 1. The relevant register
locations are as follows.
DPL
82h
DPH
83h
DPL1
84h
DPH1
85h
DPS
86h
Low byte original DPTR
High byte original DPTR
Low byte new DPTR
High byte new DPTR
DPTR Select (lsb)
STOP MODE ENHANCEMENTS
Setting bit 1 of the Power Control Register (PCON; 87h) invokes the stop mode. Stop mode is the lowest
power state because it turns off all internal clocking. The I_CC of a standard stop mode is approximately
1A (but is specified in the Absolute Maximum Ratings section). The CPU exits stop mode from an
external interrupt or a reset condition. Internally generated interrupts are not useful since they require
clocking activity.
The DS80C310 allows a resume from stop using INT2–INT5, which are edge-triggered interrupts. An
internal crystal counter manages the startup timing. A delay of 65,536 clocks occurs to allow the crystal
time to stabilize. Software must also insert a delay of 100 machine cycles following the exit from stop
mode. This ensures stabilization of internal timing prior to time-critical software tasks such as serial port
operations or bus access to memory-mapped I/O devices.
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