DS80C310_09 Datasheet, PDF (4/22 Pages) Dallas Semiconductor – High-Speed Microcontroller

DS80C310
PDIP
10–17
18, 19
20
21
22
23
24
25
26
27
28
PIN
PLCC
11,
13–19
20, 21
1, 22,
23
24
25
26
27
28
29
30
31
TQFP
5, 7–13
14, 15
16, 17,
39
18
19
20
21
22
23
24
25
NAME
FUNCTION
Port 3 (I/O). Port 3 functions as both an 8-bit bidirectional I/O port
and an alternate functional interface for external Interrupts, Serial
Port 0, Timer 0 and 1 Inputs, RD and WR strobes. The reset
condition of Port 3 is with all bits at logic 1. In this state, a weak
pullup holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will overcome
the weak pullup. When software writes a 0 to any port pin, the
DS80C310 will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has
been at 0 will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong driver turns
off, the port once again becomes both the output high and input
state. The alternate modes of Port 3 are as follows:
P3.0–P3.7
XTAL2,
XTAL1
PIN
PORT ALTERNATE
PDIP PLCC TQFP
FUNCTION
10 11
5
P3.0
RXD0
Serial Port 0
Input
11 13
7
P3.1
TXD0
Serial Port 0
Output
12 14
8
P3.2
INT0
External Interrupt
0
13 15
9
P3.3
INT1
External Interrupt
1
14 16
10 P3.4
T0
Timer 0 External
Input
15 17
11 P3.5
T1
Timer 1 External
Input
16 18
12 P3.6
External Data
WR
Memory Write
Strobe
17 19
13 P3.7
External Data
RD
Memory Read
Strobe
Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for
parallel resonant, AT-cut crystals. XTAL1 also acts as an input in
the event that an external clock source is used in place of a crystal.
XTAL2 serves as the output of the crystal amplifier.
GND Digital Circuit Ground
A8 (P2.0)
A9 (P2.1)
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
Address Outputs (Port 2) (Output). Port 2 serves as the MSB for
external addressing. P2.7 is A15 and P2.0 is A8. The DS80C310
automatically places the MSB of an address on P2 for external ROM
and RAM access. Although Port 2 can be accessed like an ordinary
I/O port, the value stored on the Port 2 latch is never seen on the pins
(due to memory access). Therefore, writing to Port 2 in software is
only useful for the instructions MOVX A, @ Ri or MOVX @ Ri, A.
These instructions use the Port 2 internal latch to supply the external
address MSB; the Port 2 latch value is supplied as the address
information.
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