DS26401 Datasheet, PDF (85/309 Pages) Dallas Semiconductor – Octal T1/E1/J1 Framer

DS26401 Octal T1/E1/J1 Framer
8.17 Receive SLC-96 Operation
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message
fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC-
96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm,
maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR–TSY–000008.
To enable the DS26401 to synchronize onto an SLC-96 pattern, the following configuration should be used:
§ Set to D4 framing mode (RCR1.5 = 1)
§ Set to cross-couple Ft and Fs bits (RCR1.3 = 1)
§ Enable SLC-96 synchronizer (RCR2.4 = 1)
§ Set to minimum sync time (RCR1.7 = 0)
The status bit RSLC96 located at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit indicates
when the framer has received the 12-bit Fs-alignment pattern and updated the data-link registers RSLC1–RSLC3
with the latest message data from the incoming data stream. Once the RSLC96 bit is set, the user has 2ms to
retrieve the most recent message data from the RSLC1/2/3 registers. Note that RSLC96 is not set if the DS26401 is
unable to detect the 12-bit SLC-96 alignment pattern.
Register Name:
Register Description:
Register Address:
RSLC1, RSLC2, RSLC3
Receive SLC96 Data Link Registers
064h, 065h, 066h [+ (200h x n) : where n = 0 to 7, for Ports 1 to 8]
(MSB)
C8
C7
M2
M1
S=1
S4
C6
C5
C4
C3
S=0 S=1 S=0
C11
S3
S2
S1
A2
(LSB)
C2
C1 RSLC1
C10
C9 RSLC2
A1
M3 RSLC3
85