DS26401 Datasheet, PDF (124/309 Pages) Dallas Semiconductor – Octal T1/E1/J1 Framer

DS26401 Octal T1/E1/J1 Framer
9.11 T1 Transmit Channel Blocking Registers
The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking
Registers (TCBR1 / TCBR2 / TCBR3 / TCHR4) control RCHBLK and TCHBLK pins respectively. The RCHBLK and
TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels.
When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire
corresponding channel time.
Register Name:
Register Description:
Register Address:
TCBR1, TCBR2, TCBR3, TCBR4
Transmit Channel Blocking Registers
1C4h, 1C5h, 1C6h, 1C7h [+ (200h x n) : where n = 0 to 7, for Ports 1
to 8]
(MSB)
CH8
CH16
CH24
CH32
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
(LSB)
CH1
CH9
CH17
CH25/Fbit
TCBR1
TCBR2
TCBR3
TCBR4*
Bits 0 to 7 / Transmit Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32)
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
In T1 mode, the LSB of TCBR4 determines whether or not the TCHBLK signal will pulse high during
the F-Bit time:
TCBR4.0 = 0, do not pulse TCHBLK during the F-Bit
TCBR4.0 = 1, pulse TCHBLK during the F-Bit
In this mode, TCBR4.1 to TCBR4.7 should be set to 0.
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