DS5002FP_06 Datasheet, PDF (8/25 Pages) Dallas Semiconductor – Secure Microprocessor Chip

DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING
(V_CC = 5V ±10%, T_A = 0°C to +70°C.) (Figure 6)
#
PARAMETER
40
Delay to Byte-Wide Address Valid from CE1,
CE2, or CE1N Low During Op Code Fetch
41 Pulse Width of CE1–4, PE1–4, or CE1N
42
Byte-Wide Address Hold After CE1, CE2, or
CE1N High During Op Code Fetch
43
Byte-Wide Data Setup to CE1, CE2, or CE1N
High During Op Code Fetch
SYMBOL
t_CE1LPA
t_CEPW
t_CE1HPA
t_OVCE1H
MIN
4t_CLK - 35
2t_CLK - 20
1t_CLK + 40
MAX
30
44
Byte-Wide Data Hold After CE1, CE2, or CE1N
High During Op Code Fetch
t_CE1HOV
0
45
Byte-Wide Address Hold After CE1–4, PE1–4, or
CE1N High During MOVX
t_CEHDA
4t_CLK - 30
46
Delay from Byte-Wide Address Valid CE1–4,
PE1–4, or CE1N Low During MOVX
t_CELDA
4t_CLK - 35
47
Byte-Wide Data Setup to CE1–4, PE1–4, or
CE1N High During MOVX (Read)
t_DACEH
1t_CLK + 40
48
Byte-Wide Data Hold After CE1–4, PE1–4, or
CE1N High During MOVX (Read)
t_CEHDV
0
49
Byte-Wide Address Valid to R/W Active During
MOVX (Write)
t_AVRWL
3t_CLK - 35
50
Delay from R/W Low to Valid Data Out During
MOVX (Write)
t_RWLDV
20
51
Valid Data Out Hold Time from CE1–4, PE1–4, or
CE1N High
t_CEHDV
1t_CLK - 15
52 Valid Data Out Hold Time from R/W High
53 Write Pulse Width (R/W Low Time)
t_RWHDV
t_RWLPW
0
6t_CLK - 20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 6. Byte-Wide Bus Timing
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