DS1481 Datasheet, PDF (8/10 Pages) Dallas Semiconductor – 1.Wire Bus Master with Overdrive

DS1481
DETAILED PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Vcc
DC supply voltage.
ENI
I
Chip enable, driven low to begin 1–wire I/O.
O1/BSY1
O
Driven low during time slot (to indicate a DS1481 busy condition). Set to state
of I1 after time slot has finished. O1/BSY1 will go low after D/CLK goes low if
sample of I/O communication was low. Returns to state of I1 when ENI goes
back high (see Figure 1).
O2/BSY2
O
Driven low during time slot (to indicate a DS1481 busy condition). Set to state
of I2 after time slot has finished. O2/BSY2 will go low after D/CLK goes low if
sample of I/O communication was low. Returns to state of I2 when ENI goes
back high (see Figure 1).
D/CLK
I
Data/Clock pin. Used to specify type of time slot before communication begins.
After the time slot has been completed this pin is driven low in order to solicit
the result of the time slot.
RES
I
Set low (before ENI is driven low) to specify that a reset pulse should be gener-
ated on the I/O pin.
GND
System ground.
I1
I
Can be connected to the O1/BSY1 of another DS1481. May also be connected
to parallel port printer’s BUSY signal. Internally pulled high via a weak resistor.
I2
I
Can be connected to the O2/BSY2 of another DS1481. Can also be connected
to a parallel port printer SELECT OUT signal. Internally pulled high via a weak
resistor.
ENO
O
Set to ENI if not the last part on port. Open drain output with weak internal
pull–up resistor.
I/O
I/O
1–wire I/O line. Bi–directional line with open drain output.
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