DS1481 Datasheet, PDF (6/10 Pages) Dallas Semiconductor – 1.Wire Bus Master with Overdrive

DS1481
TIMING DIAGRAM: HOST INTERFACE Figure 4
ENI
D/CLK
RES
VALID
VALID
O1/BSY1
O2/BSY2
READ 0
(I/O)
READ 1
(I/O)
WRITE 1
(I/O)
t_BLB
t_SIO
t_SIO = 8 µs (TYPICAL), t_BLB = 60 µs (MINIMUM)
t_SIO = 2 µs (MAXIMUM), t_BLB = 6 µs (MINIMUM)
READ O, READ 1, WRITE 1 BIT TIME SLOTS
(OD = 0)
(OD = 1)
TIMING DIAGRAM: HOST INTERFACE Figure 5
ENI
D/CLK
RES
VALID
VALID
O1/BSY1
O2/BSY2
WRITE 0
(I/O)
t_BLB
t_BLB = 60 µs (MINIMUM)
t_BLB = 6 µs (MINIMUM)
(OD = 0)
(OD = 1)
WRITE 0 TIME SLOT
021798 6/10