DS1481 Datasheet, PDF (7/10 Pages) Dallas Semiconductor – 1.Wire Bus Master with Overdrive

TIMING DIAGRAM: HOST INTERFACE Figure 6
ENI
D/CLK
VALID
RES
VALID
O1/BSY1
t_BLR
O2/BSY2
RESET
(I/O)
t_PDH = 2 µs (TYPICAL)
t_BLR = 960 µs (MINIMUM)
t_{BLB =} 96 µs (MINIMUM)
1–WIRE RESET
(OD = 0)
(OD = 1)
TIMING DIAGRAM: HOST INTERFACE Figure 7
ENI
D/CLK
RES
O1/BSY1
VALID
VALID
O2/BSY2
TOGGLE OVERDRIVE MODE
DS1481
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