DS1200 Datasheet, PDF (7/7 Pages) Dallas Semiconductor – Serial RAM Chip

AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL MIN
Data to CLK Setup
t_DC
35
Data to CLK Hold
tCDH
40
Data to CLK Delay
t_CDD
CLK Low Time
t_CL
125
CLK High Time
t_CH
125
CLK Frequency
f_CLK
DC
CLK Rise and Fall
t_R, t_F
RST to Clock Setup
t_CC
1
CLK to RST Hold
t_CCH
40
RST Inactive Time
t_CWH
125
RST to I/O High-Z
t_CDZ
DS1200
(0ºC to +70ºC; V_CC = 5V ± 10%)
TYP MAX UNITS NOTES
ns
3, 9
ns
3, 9
125
ns 3, 4, 6, 9
ns
3, 9
ns
3, 9
4.0
MHz
3, 9
500
ns
9
µs
3, 9
ns
3, 9
ns 3, 9, 14
50
ns
3, 9
NOTES:
1) All voltages and resistances are referenced to ground.
2) Input levels apply to CLK, DQ, and RST while V_CC is not connected to the tag, then RST input
reverts to V_IHE.
3) Measured at V_IH = 2.0 or V_IL = 0.8V and 10ns maximum rise and fall time.
4) Measured at V_OH = 2.4V and V_OL = 0.4V.
5) For CLK, DQ, RST , and V_CC at 5V.
6) Load capacitance = 50pF.
7) Applies to RST when V_CC < 3.8V.
8) Measured with outputs open.
9) Measured at VIH of RST greater than or equal to 3.8V when RST supplies power.
10) Logic 1 maximum is V_CC + 0.3V if the V_CC pin supplies power and RST +0.3V if the RST pin
supplies power.
11) RST logic 1 maximum is V_CC + 0.3V if the V_CC pin supplies power and 5.5V maximum if RST
supplies power.
12) Each DS1200 is marked with a four-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected t_DR is defined as starting at the date of
manufacture.
13) Average AC RST current can be determined using the following formula:
I_TOTAL = 2 + I_LOAD DC + (4 x 10^-3)(CL + 140)f
I_TOTAL and I_LOAD are in mA; CL is in pF; f is in MHz.
Applying the above formula, a load capacitance of 50pF running at a frequency of 4.0MHz gives an
I_TOTAL current of 5mA.
14) When RST is supplying power, t_CWH must be increased to 100ms.
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