DS1200 Datasheet, PDF (2/7 Pages) Dallas Semiconductor – Serial RAM Chip

Figure 1. ELECTRONIC TAG BLOCK DIAGRAM
DS1200
Figure 2. ADDRESS/COMMAND
765432107654321076543210
RRRRRRRR
B 0 0 0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 A0
WWWWWWWW
B-BURST
R-READ
W-WRITE
BYTE 3
BYTE 2
BYTE 1
OPERATION
The block diagram (Figure 1) illustrates the main elements of the device: shift register, control logic,
NV RAM, and power switch. To initiate a memory cycle, RST is taken high and 24 bits are loaded into
the shift register, providing both address and command information. Each bit is input serially on the
rising edge of the CLK input. Seven address bits specify one of the 128 RAM locations. The remaining
command bits specify read/write and byte/burst mode. After the first 24 clocks, which load the shift
register, additional clocks will output data for a read or input data for a write. The number of clock pulses
equal 24 plus 8 for byte mode or 24 plus 1024 for burst mode.
For hardwired applications, active power is supplied by the V_CC pin. Alternatively, for user-insertable
applications, power can be supplied by the RST pin.
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