DS1217M_03 Datasheet, PDF (6/8 Pages) Dallas Semiconductor – Nonvolatile Read/Write Cartridge

DS1217M Nonvolatile Read/Write Cartridge
DC TEST CONDITIONS
Outputs Open
t Cycle = 250ns
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
DETAILED DESCRIPTION
Read Mode
The DS1217M executes a read cycle whenever WE (write enable) is inactive (high) and CE (cartridge enable) is
active (low). The unique address specified by the address inputs (A0–A14) defines which byte of data is to be
accessed. Valid data will be available to the eight data I/O pins within t_ACC (access time) after the last address input
signal is stable, provided that CE (cartridge enable) and OE (output enable) access times are also satisfied. If OE
and CE times are not satisfied, then data access must be measured from the late occurring signal (CE or OE) and
the limiting parameter is either t_CO for CE or t_OE for OE rather than address access. Read cycles can only occur
when V_CC is greater than 4.5V. When V_CC is less than 4.5V, the memory is inhibited and all accesses are ignored.
Write Mode
The DS1217M is in the write mode whenever both the WE and CE signals are in the active (low) state after address
inputs are stable. The last occurring falling edge of either CE or WE will determine the start of the write cycle. The
write cycle is terminated by the first rising edge of either CE or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high state for a minimum recovery time (t_WR) before another cycle
can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention.
However, if the output bus has been enabled (CE and OE active), then WE will disable the outputs in t_ODW from its
falling edge. Write cycles can only occur when V_CC is greater than 4.5 V. When V_CC is less than 4.5Vs, the memory
is write-protected.
Data Retention Mode
The nonvolatile cartridge provides full functional capability for V_CC greater than 4.5V and guarantees write
protection for V_CC less than 4.5V. Data is maintained in the absence of V_CC without any additional support circuitry.
The DS1217M constantly monitors V_CC. Should the supply voltage decay, the RAM is automatically write-protected
below 4.5V. As V_CC falls below approximately 3.0V, the power switching circuit connects a lithium energy source to
RAM to retain data. During power-up, when V_CC rises above approximately 3.0V, the power switching circuit
connects the external V_CC to the RAM and disconnects the lithium energy source. Normal RAM operation can
resume after V_CC exceeds 4.5V.
The DS1217M checks battery status to warn of potential data loss. Each time that V_CC power is restored to the
cartridge, the battery voltage is checked with a precision comparator. If the battery supply is less than 2.0V, the
second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after
power-up to any location in memory, recording that memory location content. A subsequent write cycle can then be
executed to the same memory location, altering data. If the next read cycle fails to verify the written data, the
contents of the memory are questionable.
In many applications, data integrity is paramount. The cartridge thus has redundant batteries and an internal
isolation switch that provides for the connection of two batteries. During battery backup time, the battery with the
highest voltage is selected for use. If one battery fails, the other will automatically take over. The switch between
batteries is transparent to the user. A battery status warning will occur only if both batteries are less than 2.0V.
Bank Switching
Bank switching is accomplished via address lines A8, A9, A10, and A11. Initially, on power-up all banks are
deselected so that multiple cartridges can reside on a common bus. Bank switching requires that a predefined
pattern of 64 bits is matched by sequencing 4 address inputs (A8 through A11) 16 times while ignoring all other
address inputs. Prior to entering the 64-bit pattern, which will set the band switch, a read cycle of 1111 (address
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