DS80C310_1 Datasheet, PDF (5/21 Pages) Dallas Semiconductor – High-Speed Micro

DS80C310
COMPATIBILITY
The DS80C310 is a fully static CMOS 8051 compatible
microcontroller designed for high performance. In most
cases the DS80C310 can drop into an existing socket
for the 80C31 or 80C32 to improve the operation signifi-
cantly. In general, software written for existing 8051
based systems works without modification on the
DS80C310. The exception is critical timing since the
High–Speed Micro performs its instructions much faster
than the original for any given crystal selection. The
DS80C310 runs the standard 8051 family instruction
set and is pin compatible with DIP, PLCC or TQFP pack-
ages. The DS80C310 is a streamlined version of the
DS80C320. It maintains upward compatibility but has
fewer peripherals.
The DS80C310 provides three 16–bit timer/counters, a
full–duplex serial port, and 256 bytes of direct RAM. I/O
ports have the same operation as a standard 8051 prod-
uct. Timers will default to a 12 clock per cycle operation
to keep their timing compatible with original 8051 family
systems. However, timers are individually program-
mable to run at the new 4 clocks per cycle if desired.
The DS80C310 provides several new hardware func-
tions that are controlled by Special Function registers. A
summary of the Special Function Registers is provided
in Table 2.
PERFORMANCE OVERVIEW
The DS80C310 features a high–speed 8051 compatible
core. Higher speed comes not just from increasing the
clock frequency, but from a newer, more efficient
design.
This updated core does not have the dummy memory
cycles that are present in a standard 8051. A conven-
tional 8051 generates machine cycles using the clock
frequency divided by 12. In the DS80C310, the same
machine cycle takes four clocks. Thus the fastest
instruction, 1 machine cycle, executes three times
faster for the same crystal frequency. Note that these
are identical instructions. The majority of instructions on
the DS80C310 will see the full 3 to 1 speed improve-
ment. Some instructions will get between 1.5 and 2.4 to
1 improvement. All instructions are faster than the origi-
nal 8051.
The numerical average of all opcodes gives approxi-
mately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instruc-
tions used. Speed sensitive applications would make
the most use of instructions that are three times faster.
However, the sheer number of 3 to 1 improved opcodes
makes dramatic speed improvements likely for any
code. These architecture improvements and 0.8 µm
CMOS produce a peak instruction cycle in 121 ns (8.25
MIPs). The Dual Data Pointer feature also allows the
user to eliminate wasted instructions when moving
blocks of memory.
INSTRUCTION SET SUMMARY
All instructions in the DS80C310 perform the same
functions as their 8051 counterparts. Their effect on
bits, flags, and other status functions is identical. How-
ever, the timing of each instruction is different. This
applies both in absolute and relative number of clocks.
For absolute timing of real–time events, the timing of
software loops can be calculated using a table in the
High–Speed Microcontroller User’s Guide. However,
counter/timers default to run at the older 12 clocks per
increment. In this way, timer–based events occur at the
standard intervals with software executing at higher
speed. Timers optionally can run at 4 clocks per incre-
ment to take advantage of faster processor operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the
DS80C310, the MOVX instruction takes as little as two
machine cycles or eight oscillator cycles but the “MOV
direct, direct” uses three machine cycles or 12 oscillator
cycles. While both are faster than their original counter-
parts, they now have different execution times. This is
because the DS80C310 usually uses one instruction
cycle for each instruction byte. The user concerned with
precise program timing should examine the timing of
each instruction for familiarity with the changes. Note
that a machine cycle now requires just four clocks, and
provides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the orig-
inal architecture, all were one or two cycles except for
MUL and DIV. Refer to the High–Speed Microcontroller
User’s Guide for details and individual instruction tim-
ing.
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