DS80C310_1 Datasheet, PDF (3/21 Pages) Dallas Semiconductor – High-Speed Micro

DS80C310
PIN DESCRIPTION Table 1
DIP PLCC TQFP SIGNAL
NAME
40
44
38
20 22, 23, 16, 17,
1
39
V_CC
GND
9
10
4
RST
18
20
14
19
21
15
XTAL2
XTAL1
29
32
26
PSEN
30
33
27
ALE
39
43
37
AD0 (P0.0)
38
42
36
AD1 (P0.1)
37
41
35
AD2 (P0.2)
36
40
34
AD3 (P0.3)
35
39
33
AD4 (P0.4)
34
38
32
AD5 (P0.5)
33
37
31
AD6 (P0.6)
32
36
30
AD7 (P0.7)
1–8
2–9 40–44 P1.0–P1.7
1–3
DESCRIPTION
V_CC – +5V.
GND – Digital circuit ground.
RST – Input. The RST input pin contains a Schmitt voltage input
to recognize external active high reset inputs. The pin also
employs an internal pull–down resistor to allow for a combination
of wired OR external Reset sources.
XTAL1, XTAL2 – The crystal oscillator pins XTAL1 and XTAL2
provide support for parallel resonant, AT cut crystals. XTAL1 acts
also as an input in the event that an external clock source is used
in place of a crystal. XTAL2 serves as the output of the crystal
amplifier.
PSEN – Output. The Program Store Enable output. This signal
is commonly connected to external ROM memory as a chip
enable. PSEN is active low. PSEN is driven high when data
memory (RAM) is being accessed through the bus and during a
reset condition.
ALE – Output. The Address Latch Enable output functions as a
clock to latch the external address LSB from the multiplexed
address/data bus on Port 0. This signal is commonly connected
to the latch enable of an external 373 family transparent latch.
ALE is forced high when the DS80C310 is in a Reset condition.
AD0–7 (Port 0) – I/O. Port 0 is the multiplexed address/data bus.
During the time when ALE is high, the LSB of a memory address
is presented. When ALE falls to a logic 0, the port transitions to
a bidirectional data bus. This bus is used to read external ROM
and read/write external RAM memory or peripherals. Port 0 has
no true port latch and can not be written directly by software. The
reset condition of Port 0 is high.
Port 1 – I/O. Port 1 functions as both an 8–bit bidirectional I/O port
and an alternate functional interface for Timer 2 I/O and new Exter-
nal Interrupts. The reset condition of Port 1 is with all bits at a logic
1. In this state, a weak pull–up holds the port high. This condition
also serves as an input mode, since any external circuit that writes
to the port will overcome the weak pull–up. When software writes
a 0 to any port pin, the DS80C310 will activate a strong pull–down
that remains on until either a 1 is written or a reset occurs. Writing
a 1 after the port has been at 0 will cause a strong transition driver
to turn on, followed by a weaker sustaining pull–up. Once the
momentary strong driver turns off, the port once again becomes
the output high (and input) state. The alternate modes of Port 1
are outlined as follows:
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