DS1644P Datasheet, PDF (5/13 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

DS1644/DS1644P
DS1644 REGISTER MAP—BANK1 Table 2
ADDRESS
DATA
B₇
B₆
B₅
B₄
B₃
B₂
B₁
B₀
7FFF
— ———————
FUNCTION
Year
00-99
7FFE
X
X
X — — — — — Month 01-12
7FFD
X
X
-
—————
Date
01-31
7FFC
X
FT X
X
X ———
Day
01-07
7FFB
X
X
——————
Hour
00-23
7FFA
X
— — — — — — — Minutes 00-59
7FF9
OSC ^{— — — — — — — Seconds 00-59}
7FF8
W
R
X
X
X
X
X
X Control
A
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
Note: All indicated “X” bits are unused but must be set to “0” during write cycles to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t_AA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (t_CEA) or at output enable access time (t_OEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before t_AA, the data
lines are driven to an intermediate state until t_AA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (t_OH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE or CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of t_WR prior to the initiation of
another read or write cycle. Data in must be valid t_DS prior to the end of write and remain valid for t_DH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t_WEZ after WE goes active.
5 of 13