DS1553 Datasheet, PDF (5/19 Pages) Maxim Integrated Products – 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM

DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
Table 2. Register Map
ADDRESS
1FFFh
1FFEh
1FFDh
1FFCh
1FFBh
1FFAh
1FF9h
1FF8h
1FF7h
1FF6h
1FF5h
1FF4h
1FF3h
1FF2h
1FF1h
1FF0h
B7
X
X
X
X
X
OSC
W
WDS
AE
AM4
AM3
AM2
AM1
Y
WF
DATA
B6
B5
B4
B3
10 Year
X
X
10 M
X
10 Date
FT
X
X
X
X
10 Hour
10 Minutes
10 Seconds
R
10 Century
BMB4 BMB3 BMB2 BMB1
Y
ABE
Y
Y
Y
10 Date
Y
10 Hours
10 Minutes
10 Seconds
Y
Y
Y
Y
AF
0
BLF
0
B2
B1
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
BMB0 RB1
Y
Y
Date
Hours
Minutes
Seconds
Y
Y
0
0
B0
RB0
Y
Y
0
FUNCTION/RANGE
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
Watchdog
Interrupts
Alarm Date
Alarm Hours
Alarm Minutes
Alarm Seconds
Unused
Flags
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
01-31
00-23
00-59
00-59
X = Unused, Read/Writable Under Write and Read Bit Control
FT = Frequency Test Bit
OSC = Oscillator Start/Stop Bit
W = Write Bit
R = Read Bit
WDS = Watchdog Steering Bit
BMB0–BMB4 = Watchdog Multiplier Bits
RB0–RB1 = Watchdog Resolution Bits
AE = Alarm Flag Enable
Y = Unused, Read/Writable Without Write and Read Bit Control
ABE = Alarm in Battery-Backup Mode Enable
AM1–AM4 = Alarm Mask Bits
WF = Watchdog Flag
AF = Alarm Flag
0 = 0 Read Only
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds register (B7 of 1FF9h). Setting it to 1 stops the oscillator; setting it to 0 starts the
oscillator. The DS1553 is shipped from Dallas Semiconductor with the clock oscillator turned off, with
the OSC bit set to 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
registers. This puts the external registers into a static state, allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h).
As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
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