DS1553 Datasheet, PDF (3/19 Pages) Maxim Integrated Products – 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM

Figure 1. Block Diagram
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Table 1. Operating Modes
VCC
CE OE WE
VIH
X
X
VCC > VPF
VIL
X
VIL
VIL
VIL
VIH
VIL
VIH
VIH
VSO < VCC <VPF
X
X
X
<VBAT
X
X
X
DQ0–DQ7
High-Z
DIN
DOUT
High-Z
High-Z
High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1553 is in read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data is available at
the data input/output (DQ) pins within t_AA after the last address input is stable, provided that CE and OE
access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of
chip-enable access (t_CEA) or at output-enable access time (t_OEA). The state of the DQ pins is controlled by
CE and OE . If the outputs are activated before t_AA, the data lines are driven to an intermediate state until
t_AA. If the address inputs are changed while CE and OE remain valid, output data remains valid for
output data hold time (t_OH) but will then go indeterminate until the next address access.
DATA WRITE MODE
The DS1553 is in write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of t_WR prior to the initiation of a subsequent
read or write cycle. Data in must be valid t_DS prior to the end of the write and remain valid for t_DH
afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
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