DS1135 Datasheet, PDF (5/6 Pages) Dallas Semiconductor – 3-in-1 High-Speed Silicon Delay Line

TEST CONDITIONS
Ambient Temperature: 25°C ±=3°C
Supply Voltage (V_CC ): 5.0V ±=0.1V
Input Pulse:
High: 3.0V ±=0.1V
Low: 0.0V ±=0.1V
Source Impedance: 50Ω=Max.
Rise and Fall Time: 3.0 ns Max. - Measured between 0.6V and 2.4V.
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load Capacitance: 15 pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
DS1135
NOTE:
The above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM
tRISE
PERIOD
tFALL
80%
20%
IN
OUT
1.5V
1.5V
tWI
tPLH
tPHL
tOR
1.5V
1.5V
tWI
tOF
1.5V
NOTES:
1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
3. Power-up time is the time from the application of power to the time stable delays are being produced
at the output.
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