DS1135 Datasheet, PDF (2/6 Pages) Dallas Semiconductor – 3-in-1 High-Speed Silicon Delay Line

LOGIC DIAGRAM Figure 1
IN
TIME DELAY
DS1135
OUT
ONE OF THREE
PART NUMBER DELAY TABLE (t_PLH , t_PHL ) Table 1
TOLERANCE OVER
DELAY PER
INITIAL
TEMP AND VOLTAGE
PART NUMBER
OUTPUT
(ns)
TOLERANCE
(Note 1)
(Note 2)
0°C to +70°C -40°C to +85°C
DS1135-5
5/5/5
±1.0 ns
±1.0 ns
±1.5 ns
DS1135-6
6/6/6
±1.0 ns
±1.0 ns
±1.5 ns
DS1135-8
8/8/8
±1.0 ns
±1.0 ns
±1.5 ns
DS1135-10
10/10/10
±1.0 ns
±1.0 ns
±1.5 ns
DS1135-12
12/12/12
±1.0 ns
±1.0 ns
±1.5 ns
DS1135-15
15/15/15
±1.0 ns
±1.5 ns
±2 ns
DS1135-20
20/20/20
±1.0 ns
±1.5 ns
±2 ns
DS1135-25
DS1135-30
25/25/25
30/30/30
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±2 ns
±2 ns
NOTES:
1. Nominal conditions are +25°C and V_CC =+5.0 volts.
2. Voltage range of 4.75 volts to 5.25 volts.
3. Delay accuracies are for both leading and trailing edges.
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1135.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution ) connected to the output. The DS1135 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
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