DS3134 Datasheet, PDF (41/203 Pages) Dallas Semiconductor – Chateau Channelized T1 And E1 And HDLC Controller

DS3134
Bits 7 to 11 / BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These 5 bits select which port has the
dedicated resources of the BERT.
00000 = Port 0
00001 = Port 1
00010 = Port 2
00011 = Port 3
00100 = Port 4
00101 = Port 5
00110 = Port 6
00111 = Port 7
01000 = Port 8
01001 = Port 9
01010 = Port 10
01011 = Port 11
01100 = Port 12
01101 = Port 13
01110 = Port 14
01111 = Port 15
10000 = Port 0 (hi speed)
10001 = Port 1 (hi speed)
10010 = n/a
10011 = n/a
10100 = n/a
10101 = n/a
10110 = n/a
10111 = n/a
11000 = n/a
11001 = n/a
11010 = n/a
11011 = n/a
11100 = n/a
11101 = n/a
11110 = n/a
11111 = n/a
Bit 12 / Receive FIFO Priority Control Bit 0 (RFPC0).
Bit 13 / Receive FIFO Priority Control Bit 1 (RFPC1).
These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest
priority to the DMA to transfer data from the FIFO to the PCI Bus. In the priority decoded scheme, the
lower the HDLC channel numbers, the higher the priority.
00 = all HDLC channels are serviced Round Robin
01 = HDLC Channels 1 & 2 are Priority Decoded; other HDLC Channels are Round Robin
10 = HDLC Channels 1 to 16 are Priority Decoded; other HDLC Channels are Round Robin
11 = HDLC Channels 1 to 64 are Priority Decoded; other HDLC Channels are Round Robin
Bit 14 / Transmit FIFO Priority Control Bit 0 (TFPC0).
Bit 15 / Transmit FIFO Priority Control Bit 1 (TFPC1).
These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest
priority to the DMA to transfer data from the PCI Bus to the FIFO. In the priority decoded scheme, the
lower the HDLC channel numbers, the higher the priority.
00 = all HDLC channels are serviced Round Robin
01 = HDLC Channels 1 & 2 are Priority Decoded; other HDLC Channels are Round Robin
10 = HDLC Channels 1 to 16 are Priority Decoded; other HDLC Channels are Round Robin
11 = HDLC Channels 1 to 64 are Priority Decoded; other HDLC Channels are Round Robin
4.3 STATUS & INTERRUPT
4.3.1 Status & Interrupt General Description of Operation
There are three status register in the device, Status Master (SM), Status for the Receive V54 Loopback
Detector (SV54), and Status for DMA (SDMA). All three registers report events in real time as they
occur by setting a bit within the register to a one. All bits that have been set within the register are cleared
when the register is read and the bit will not be set again until the event has occurred again. Each bit has
the ability to generate an interrupt at the PCI Bus via the PINTA* output signal pin and if the Local Bus is
in the Configuration Mode, then an interrupt will also be created at the LINT* output signal pin. Each
status register has an associated Interrupt Mask Register, which can allow/deny interrupts from being
generated on a bit-by-bit basis. All status remains active even if the associated Interrupt is disabled.
41 of 203