DS3134 Datasheet, PDF (132/203 Pages) Dallas Semiconductor – Chateau Channelized T1 And E1 And HDLC Controller

DS3134
The Transmit DMA will read from the Transmit Pending Queue Descriptor circular queue which data
buffers and their associated descriptors are ready for transmission. To keep track of the addresses of the
circular queue in the Transmit Pending Queue, there are a set of internal addresses within the device that
are accessed by both the Host and the DMA. On initialization, the Host will configure all of the registers
shown in Table 8.2.3A. After initialization, the DMA will only write to (i.e. change) the read pointers
and the Host will only write to the write pointers.
Empty Case
The Transmit Pending Queue is considered empty when the read and write pointers are identical.
Transmit Pending Queue Empty State
read pointer >
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
empty descriptor
< write pointer
Full Case
The Transmit Pending Queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Hence, one descriptor must always remain empty.
Transmit Pending Queue Full State
read pointer >
valid descriptor
valid descriptor
empty descriptor
valid descriptor
valid descriptor
valid descriptor
valid descriptor
< write pointer
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