DS3134 Datasheet, PDF (111/203 Pages) Dallas Semiconductor – Chateau Channelized T1 And E1 And HDLC Controller

DS3134
dword 0; Bits 0 to 15 / Descriptor Pointer. This 16-bit value is the offset from the Receive Descriptor
Base Address of a Receive Packet Descriptor that has been readied by the DMA and is available for the
host to begin processing. Note: This is index not absolute address.
dword 0; Bits 16 to 23 / HDLC Channel Number. HDLC channel number, which can be from 1 to
256.
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
dword 0; Bits 24 to 26 / Buffer Count (BUFCNT). If a HDLC channel has been configured to only
write to the Done Queue after a packet has been completely received (i.e. the Threshold field in the
Receive DMA Configuration RAM is set to 000) then BUFCNT will always be set to 000. If the HDLC
channel has been configured via the Threshold field to write to the Done Queue after a programmable
number of buffers (from 1 to 7) have been filled, then BUFCNT corresponds to the number of buffers
which have been written to Host memory. The BUFCNT will be less than the Threshold field value when
the incoming packet does not require the number of buffers specified in the Threshold field.
000 = indicates that a complete packet has been received (only used when Threshold = 000)
001 = 1 buffer has been filled
010 = 2 buffers have been filled
111 = 7 buffers have been filled
dword 0; Bits 27 to 29 / Packet Status. These three bits report the final status of an incoming packet.
They are only valid when the EOF bit is set to a one (EOF = 1).
000 = no error, valid packet received
001 = receive FIFO overflow (remainder of the packet discarded)
010 = CRC checksum error
011 = HDLC frame abort sequence detected (remainder of the packet discarded)
100 = non-aligned byte count error (not an integral number of bytes)
101 = long frame abort (max packet length exceeded; remainder of the packet discarded)
110 = PCI abort (remainder of the packet discarded)
111 = reserved state (will never occur in normal device operation)
dword 0; Bit 30 / End Of Frame (EOF). This bit will be set to a one when this Receive Descriptor is
the last one in the current descriptor chain. This indicates that a packet has been fully received or an error
has been detected which has caused a premature termination.
dword 0; Bit 31 / Valid Done Queue Descriptor (V). This bit will be set to a zero by the Receive
DMA. Instead of reading the Receive Done Queue Read Pointer to locate completed Done Queue
Descriptors, the Host can use this bit (since the DMA will set the bit to a zero when it is written into the
queue). If the latter scheme is used, the Host must set this bit to a one when the Done Queue Descriptor is
read.
The Host will read from the Receive Done Queue to find which data buffers and their associated
descriptors are ready for processing.
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