DS1689_05 Datasheet, PDF (4/36 Pages) Dallas Semiconductor – 3V/5V Serialized Real-Time Clocks with NV RAM Control

PIN
SO EDIP
24
24
25
25
26
26
27
27
28
28
—
2, 3,
19, 23
DS1689/DS1693
NAME
SQW
V_CCO
V_CCI
CEO
CEI
N.C.
FUNCTION
Square-Wave Output. The SQW pin can output a signal from one of
13 taps provided by the 15 internal divider stages of the real time
clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can
be turned on and off using the SQWE bit in Register B. A 32kHz
SQW signal is output when SQWE = 1, the Enable 32kHz (E32K)
bit in extended register 04BH is logic 1, and V_CC is above V_PF. A
32kHz square wave is also available when V_CC is less than V_PF if
E32K = 1, ABE = 1, and voltage is applied to V_BAUX.
External SRAM Power-Supply Output. This pin is internally
connected to V_CCI when V_CCI is within nominal limits. However,
during power fail, V_CCO is internally connected to the V_BAT or V_BAUX
(whichever is larger). For 5V operation, switchover from V_CCI to the
backup supply occurs when V_CCI drops below the larger of V_BAT and
V_BAUX. For 3V operation, switchover from V_CCI to the backup supply
occurs at V_PF if V_PF is less than V_BAT and V_BAUX. If V_PF is greater
than V_BAT and V_BAUX, the switch from V_CCI to the backup supply
occurs when V_CCI drops below the larger of V_BAT and V_BAUX.
+3V or +5V Main Supply. DC power is provided to the device on
these pins. 5V operation is selected when the PSEL pin is at logic 1.
If PSEL is floated or at logic 0, the device is in autosense mode and
determines the correct operating voltage based on the V_CCI voltage
level.
Active-Low RAM Chip Enable Output. When power is valid, CEO
will equal CEI. When power is not valid, CEO will be driven high
regardless of CEI.
Active-Low RAM Chip Enable Input. CEI should be driven low to
enable the external RAM.
No Connection
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