DS1689_05 Datasheet, PDF (12/36 Pages) Dallas Semiconductor – 3V/5V Serialized Real-Time Clocks with NV RAM Control

DS1689/DS1693
Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency
EXT. REG. B SELECT BITS REGISTER A
E32K
RS3 RS2 RS1 RS0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
X
X
X
X
Note: RS3–RS0 determine periodic interrupt rates as listed for E32K = 0.
t_PI PERIODIC
INTERRUPT RATE
None
3.90625ms
7.8125ms
122.070µs
244.141µs
488.281µs
976.5625µs
1.953125ms
3.90625ms
7.8125ms
15.625ms
31.25ms
62.5ms
125ms
250ms
500ms
(See Note)
SQW OUTPUT
FREQUENCY
None
256Hz
128Hz
8.192kHz
4.096kHz
2.048kHz
1.024kHz
512Hz
256Hz
128Hz
64Hz
32Hz
16Hz
8Hz
4Hz
2Hz
32.768kHz
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts
that occur at a rate of greater than t_BUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within (t_PI / 2 + t_BUC) to ensure that
data is not read during the update cycle.
Figure 3. Update-Ended and Periodic Interrupt Relationship
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