DS1337 Datasheet, PDF (3/13 Pages) Dallas Semiconductor – Serial Real-Time Clock

DS1337
AC ELECTRICAL CHARACTERISTICS
(V_CC = 1.8V to 4.0V, T_A = -40°C to +85°C.)
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX UNITS
SCL Clock Frequency
f_SCL
Fast mode
Standard mode
100
Bus Free Time Between a
STOP and START Condition
Fast mode
t_BUF
Standard mode
1.3
4.7
400
kHz
100
ms
Hold Time (Repeated)
START Condition (Note 8)
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time (Notes 9, 10)
Data Setup Time (Note 11)
Rise Time of Both SDA and
SCL Signals (Note 12)
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_R
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C_B
ms
ms
ms
ms
0.9
ms
ns
300
ns
1000
Fall Time of Both SDA and
SCL Signals (Note 12)
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
t_F
t_SU:STO
C_B
Fast mode
Standard mode
Fast mode
Standard mode
(Note 12)
20 + 0.1C_B
0.6
4.0
300
ns
300
ms
400
pF
I/O Capacitance
C_I/O
10
pF
Note 1: SCL only.
Note 2: SDA, INTA, and SQW/INTB.
Note 3: ICCA—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC.
Note 4: Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC.
Note 5: SQW enabled.
Note 6: Specified with the SQW function disabled by setting INTCN = 1.
Note 7: Using recommended crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Note 10: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ³ to 250ns must then be met. This is
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is
released.
Note 12: CB—total capacitance of one bus line in pF.
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