DS1248 Datasheet, PDF (3/21 Pages) Dallas Semiconductor – 1024k NV SRAM with Phantom Clock

RAM READ MODE
DS1248/DS1248P
The DS1248 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is
active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within t_ACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable) access
times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t_CO for CE or
t_OE for OE , rather than address access.
RAM WRITE MODE
The DS1248 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE
active) then WE will disable the outputs in t_ODW from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V_CC is greater than V_PF.
However, when V_CC is below the power-fail point, V_PF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When V_CC falls below the battery switch
point, V_SO (battery supply level), device power is switched from the V_CC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V_CC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when V_CC is greater than V_PF.
When V_CC falls below V_PF, access to the device is inhibited. If V_PF is less than V_BAT, the device power is
switched from V_CC to the backup supply (V_BAT) when V_CC drops below V_PF. If V_PF is greater than V_BAT,
the device power is switched from V_CC to the backup supply (V_BAT) when V_CC drops below V_BAT. RTC
operation and SRAM data are maintained from the battery until V_CC is returned to nominal levels.
All control, data, and address signals must be powered down when V_CC is powered-down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the
CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer to
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