DS1110 Datasheet, PDF (3/8 Pages) Dallas Semiconductor – 10-Tap Silicon Delay Line

10-Tap Silicon Delay Line
CAPACITANCE
(TA = +25°C.)
PARAMETER
Input Capacitance
SYMBOL
C_IN
CONDITIONS
MIN TYP MAX UNITS
5
10
pF
Note 1: All voltages are referenced to ground.
Note 2: Measured with outputs open.
Note 3: Initial tolerances are ± with respect to the nominal value at +25°C and V_CC = 5.0V for both leading and trailing edges.
Note 4: Temperature and voltage tolerances are with respect to the actual delay measured over stated temperature range and a 4.75V
to 5.25V range.
Note 5: Intermediate delay values are available on a custom basis.
Note 6: See Test Conditions section.
Note 7: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other
taps also slow down; tap 3 can never be faster than tap 2.
Note 8: Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.)
Note 9: For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.
(V_CC = 5.0V, T_A = +25°C, unless otherwise noted.)
Typical Operating Characteristics
DS1110-500 ACTIVE CURRENT
vs. INPUT FREQUENCY
40
35
30
25
20
15
10
5
0
0.1
15pF LOAD/TAP
V_CC = 5.25V
1.0
10
FREQUENCY (MHz)
200
180
160
140
120
100
80
60
40
20
0
0.1
DS1110-50 ACTIVE CURRENT
vs. INPUT FREQUENCY
15pF LOAD/TAP
V_CC = 5.25V
1.0
10
100
FREQUENCY (MHz)
DS1110-500 TAP 10 DELAY
vs. TEMPERATURE
575
550
525
500
475
450
425
-40
500kHz INPUT
-15
10
35
60
85
TEMPERATURE (°C)
DS1110-50 TAP 10 DELAY
vs. TEMPERATURE
54
53
52
51
50
49
48
47
46
-40 -15
10
35
60
85
TEMPERATURE (°C)
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