DS2156 Datasheet, PDF (239/262 Pages) Dallas Semiconductor – T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

DS2156
Figure 34-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic
Store Enabled)
RSYSCLK
RSER¹
RSYNC²
RMSYNC
RSYNC³
RCHCLK
RCHBLK ⁴
CHANNEL 23/31
LSB MSB
CHANNEL 24/32
LSB F MSB
CHANNEL 1/2
Note 1: Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link,
etc.) and the F-bit position is added (forced to on 1).
Note 2: RSYNC in the output mode (IOCR1.4 = 0).
Note 3: RSYNC in the input mode (IOCR1.4 = 1).
Note 4: RCHBLK is programmed to block channel 24.
Figure 34-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic
Store Enabled)
RSYSCLK
RSER
RSYNC¹
RMSYNC
RSYNC²
RSIG
RCHCLK
RCHBLK ³
CHANNEL 31
LSB MSB
CHANNEL 32
LSB MSB
CHANNEL 1
CHANNEL 31
ABCD
CHANNEL 32
ABCD
CHANNEL 1
Note 4
Note 1: RSYNC is in the output mode (IOCR1.4 = 0).
Note 2: RSYNC is in the input mode (IOCR1.4 = 1).
Note 3: RCHBLK is programmed to block channel 1.
Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.
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