DS2156 Datasheet, PDF (219/262 Pages) Dallas Semiconductor – T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

DS2156
Register Name:
Register Description:
Register Address:
ESIBCR2
Extended System Information Bus Control Register 2
B1h
Bit #
7
6
5
4
3
2
1
0
Name
— ESI4SEL2 ESI4SEL1 ESI4SEL0 — ESI3SEL2 ESI3SEL1 ESI3SEL0
Default 0
0
0
0
0
0
0
0
Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be
output when the DS2156 decodes an ESI3 address during a bus read operation.
ESI3SEL2
0
0
0
0
1
1
1
1
ESI3SEL1
0
0
1
1
0
0
1
1
ESI3SEL0
0
1
0
1
0
1
0
1
Status Output
(T1 Mode)
RBL
RYEL
LUP
LDN
SIGCHG
ESSLIP
—
—
Status Output
(E1 Mode)
RUA1
RRA
RDMA
V52LNK
SIGCHG
ESSLIP
—
—
Bit 3/Unused, must be set to 0 for proper operation
Bits 4 to 6/Address ESI4 Data-Output Select (ESI4SEL0 to ESI4SEL2). These bits select what status is to be
output when the DS2156 decodes an ESI4 address during a bus read operation.
ESI4SEL2
0
0
0
0
1
1
1
1
ESI4SEL1
0
0
1
1
0
0
1
1
ESI4SEL0
0
1
0
1
0
1
0
1
Status Output
(T1 Mode)
RBL
RYEL
LUP
LDN
SIGCHG
ESSLIP
—
—
Status Output
(E1 Mode)
RUA1
RRA
RDMA
V52LNK
SIGCHG
ESSLIP
—
—
Bit 7/Unused, must be set to 0 for proper operation
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