DS87C520MCL Datasheet, PDF (21/44 Pages) Dallas Semiconductor – EPROM/ROM High-Speed Microcontrollers

DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
PERIPHERAL OVERVIEW
The DS87C520/DS83C520 provide several of the most commonly needed peripheral functions in micro-
computer-based systems. These new functions include a second serial port, power-fail reset, power-fail
interrupt, and a programmable watchdog timer. These are described in the following paragraphs. More
details are available in the High-Speed Microcontroller User’s Guide.
SERIAL PORTS
The DS87C520/DS83C520 provide a serial port (UART) that is identical to the 80C52. In addition it
includes a second hardware serial port that is a full duplicate of the standard one. This port optionally
uses pins P1.2 (RXD1) and P1.3 (TXD1). It has duplicate control functions included in new SFR
locations.
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The
second serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) to the original. The new
serial port can only use Timer 1 for timer generated baud rates.
TIMER RATE CONTROL
There is one important difference between the DS87C520/DS83C520 and 8051 regarding timers. The
original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The
DS87C520/DS83C520 architecture normally uses four clocks per machine cycle. However, in the area of
timers and serial ports, the DS87C520/DS83C520 will default to 12 clocks per cycle on reset. This allows
existing code with real-time dependencies such as baud rates to operate properly.
If an application needs higher speed timers or serial baud rates, the user can select individual timers to run
at the 4-clock rate. The Clock Control register (CKCON;8Eh) determines these timer speeds. When the
relevant CKCON bit is a logic 1, the DS87C520/DS83C520 use 4 clocks per cycle to generate timer
speeds. When the bit is a 0, the DS87C520/DS83C520 use 12 clocks for timer speeds. The reset condition
is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0.
Unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are
independent.
POWER-FAIL RESET
The DS87C520/DS83C520 use a precision bandgap voltage reference to decide if V_CC is out of tolerance.
While powering up, the internal monitor circuit maintains a reset state until V_CC rises above the V_RST
level. Once above this level, the monitor enables the crystal oscillator and counts 65,536 clocks. It then
exits the reset state. This power-on reset (POR) interval allows time for the oscillator to stabilize.
A system needs no external components to generate a power-related reset. Anytime V_CC drops below
V_RST, as in power failure or a power drop, the monitor will generate and hold a reset. It occurs
automatically, needing no action from the software. Refer to the Electrical Specifications section for the
exact value of V_RST.
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