DS1672 Datasheet, PDF (2/13 Pages) Dallas Semiconductor – Low Voltage Serial Timekeeping Chip

DS1672 BLOCK DIAGRAM Figure 1
X1
X2
OSCILLATOR
AND DIVIDER
V_CC
V_BACKUP
GND
RST
SCL
SDA
POWER
CONTROL
SERIAL BUS
INTERFACE
CONTROL
LOGIC
ADDRESS
REGISTER
DS1672
32-BIT
COUNTER
(4 BYTES)
CONTROL
TRICKLE CHARGER
ADDRESS MAP
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h - 03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Figure 2. If the master continues to send or request more data after the address pointer has reached
05h, the address pointer will wrap around to location 00h.
DS1672 REGISTERS Figure 2
Address B7
B6
B5
B4
B3
B2
B1
B0
Function
00h
Counter
Byte 1
01h
Counter
Byte 2
02h
Counter
Byte 3
03h
Counter
Byte 4
04h
EOSC
Control
05h
TCS TCS TCS TCS DS
DS
RS
RS
Trickle
Charger
DATA RETENTION MODE
The device is fully accessible and data can be written and ready only when V_CC is greater than V_PF.
However, when V_CC falls below V_PF, (point at which write protection occurs) the internal clock registers
are blocked from any access. If V_PF is less than V_BACKUP, the device power is switched from V_CC to
V_BACKUP when V_CC drops below V_PF. If V_PF is greater than V_BACKUP, the device power is switched from
V_CC to V_BACKUP when V_CC drops below V_BACKUP. The registers are maintained from the V_BACKUP source
until V_CC is returned to nominal levels.
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