DS1672 Datasheet, PDF (11/13 Pages) Dallas Semiconductor – Low Voltage Serial Timekeeping Chip

POWER-UP DOWN CHARACTERISTICS
PARAMETER
SYMBOL MIN
V_CC Detect to RST (V_CC Falling)
V_CC Detect to RST (V_CC Rising)
V_CC Fall Time; V_PF(MAX) to V_PF(MIN)
t_RPD
t_RPU
t_F
300
V_CC Rise Time; V_PF(MIN) to V_PF(MAX)
t_R
0
TYP
250
DS1672
(-40°C to +85°C)
MAX UNITS NOTES
10
µs
ms
6
µs
µs
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write
protection.
NOTES:
1. All voltages are referenced to ground.
2. After this period, the first clock pulse is generated.
3. A device must internally provide a hold time of at least 300 ns for the SDA signal (referenced to the
V_IHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
4. The maximum t_HD:DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the
SCL signal.
5. C_B - total capacitance of one bus line in pF.
6. If the EOSC bit in the Control Register is set to logic 1, t_RPU is equal to 250 ms plus the start-up time
of the crystal oscillator.
7. I_CCA specified with SCL clocking at max frequency (400 kHz).
8. I_CCS specified with V_CC = 3.3V and SDA, SCL=3.3V.
9. I_CCS specified with V_CC = 3.0V and SDA, SCL=3.0V.
10. I_CCS specified with V_CC = 2.0V and SDA, SCL=2.0V.
11. A fast mode device can be used in a standard mode system, but the requirement t_SU:DAT >= to 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line t_R max + t_SU:DAT = 1000+250 = 1250 ns before the SCL line is released.
12. I_OSC specified with V_CC = 0V, V_BACKUP =3.6V and oscillator enabled.
13. I_BACKUP specified with V_CC = 0V, V_BACKUP =3.6V and oscillator disabled.
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