DS1339 Datasheet, PDF (15/18 Pages) Dallas Semiconductor – Serial Real-Time Clock

Figure 7. Programmable Trickle Charger
V_CC
DS1339 I²C Serial Real-Time Clock
R1
250W
R2
2kW
R3
4kW
V_BACKUP
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
TCS3 TCS2 TCS1 TCS0 DS1
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3
DS0 ROUT1 ROUT0
BIT 2 BIT 1 BIT 0
TRICKLE CHARGE REGISTER
TCS0-3 = TRICKLE CHARGER SELECT
DS0-1 = DIODE SELECT
ROUT0-1 = RESISTOR SELECT
I²C SERIAL DATA BUS
The DS1339 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339
operates as a slave on the I²C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast
mode (400kHz cycle rate) are defined. The DS1339 works in both modes. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 8):
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.
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