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DS1689 Datasheet, PDF (11/32 Pages) Dallas Semiconductor – 3-Volt/5-Volt Serialized Real-Time Clock with NV RAM Control
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PERIODIC INTERRUPT RATE AND
SQUARE WAVE OUTPUT FREQUENCY Table 2
EXT. REG. B SELECT BITS REGISTER A
tPI PERIODIC
E32K
RS3 RS2 RS1 RS0 INTERRUPT RATE
0
0
0
0
0
None
0
0
0
0
1
3.90625 ms
0
0
0
1
0
7.8125 ms
0
0
0
1
1
122.070 ms
0
0
1
0
0
244.141 ms
0
0
1
0
1
488.281 ms
0
0
1
1
0
976.5625 ms
0
0
1
1
1
1.953125 ms
0
1
0
0
0
3.90625 ms
0
1
0
0
1
7.8125 ms
0
1
0
1
0
15.625 ms
0
1
0
1
1
31.25 ms
0
1
1
0
0
62.5 ms
0
1
1
0
1
125 ms
0
1
1
1
0
250 ms
0
1
1
1
1
500 ms
1
X
X
X
X
*
*RS3-RS0 determine periodic interrupt rates as listed for E32K=0.
DS1689/DS1693
SQW OUTPUT
FREQUENCY
None
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
32.768 kHz
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts
that occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within (tPI / 2+tBUC) to ensure that data
is not read during the update cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
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