DS1689 Datasheet, PDF (10/32 Pages) Dallas Semiconductor – 3-Volt/5-Volt Serialized Real-Time Clock with NV RAM Control

DS1689/DS1693
A pattern of 01X in the DV2, DV1, and DV0, bits respectively, will turn the oscillator on and enable the
countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these
bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1. A pattern
of 11X will turn the oscillator on, but the oscillator’s countdown chain will be held in reset, as it was in
the DS1287. Any other bit combination for DV2 and DV1 will keep the oscillator off.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once
every 122 ms. This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same RS3-0 bits in Register A
which select the square wave frequency (see Table 2). Changing the bits affects both the square wave
frequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE
bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create
output intervals, or await the next needed software function.
UPDATE CYCLE
The Serialized RTC executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm and
elapsed time byte is frozen and will not update as the time increments. However, the time countdown
chain continues to update the internal copy of the buffer. This feature allows the time to maintain
accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that
time and calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 ms later. If a low is read on the UIP bit, the user has at least 244 ms before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 ms.
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