DS3171 Datasheet, PDF (108/232 Pages) Dallas Semiconductor – Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers

DS3171/DS3172/DS3173/DS3174
Table 10-31. Pseudorandom Pattern Generation
PATTERN TYPE
2⁹-1 O.153 (511 type)
2¹¹-1 O.152 and O.153
(2047 type)
2¹⁵-1 O.151
2²⁰-1 O.153
2²⁰-1 O.151 QRSS
2²³-1 O.151
BERT.PCR Register
PTF[4:0]
(hex)
PLF[4:0]
(hex)
PTS
04
08
0
QRSS
0
08
0A
0
0
0D
0E
0
0
10
13
0
0
02
13
0
1
11
16
0
0
BERT.
PCR
0x0408
0x080A
0x0D0E
0x1013
0x0253
0x1116
BERT.
SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
BERT.
SPR1
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
BERT.CR
TPIC,
RPIC
0
0
1
0
0
1
Table 10-32. Repetitive Pattern Generation
PATTERN TYPE
all 1s
all 0s
alternating 1s and 0s
double alternating and 0s
3 in 24
1 in 16
1 in 8
1 in 4
BERT.PCR Register
PTF[4:0]
(hex)
NA
PLF[4:0]
(hex) PTS
00
1
NA
00
1
NA
01
1
NA
03
1
NA
17
1
NA
0F
1
NA
07
1
NA
03
1
QRSS
0
0
0
0
0
0
0
0
BERT.
PCR
0x0020
0x0020
0x0021
0x0023
0x0037
0x002F
0x0027
0x0023
BERT.
SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF20
0xFFFF
0xFFFF
0xFFFF
BERT.
SPR1
0xFFFF
0xFFFE
0xFFFE
0xFFFC
0x0022
0x0001
0xFF01
0xFFF1
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BERT.CR.TNPL and BERT.CR.RNPL
Monitoring the BERT requires reading the BERT.SR Register which contains the Bit Error Count (BEC) bit and the
Out of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will
be one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it
receives a minimum 6 bit errors within a 64 bit window. The Receive BERT Bit Count Register (BERT.RBCR1) and
the Receive BERT Bit Error Count Register (BERT.RBECR1) will be updated upon the reception of a Performance
Monitor Update signal (e.g. BERT.CR.LPMU). This signal will update the registers with the values of the counter
since the last update and will reset the counters. See Section 10.4.5 for more details of the PMU.
10.11.4 Receive Pattern Detection
When the Receive BERT is enabled it can be used as an off-line monitor. The incoming datastream flows to the
receive BERT as well as the DS3/E3 backplane.
The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial xⁿ + x^y + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if
the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will
be forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection
performs either PRBS synchronization or repetitive pattern synchronization.
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