DS2196 Datasheet, PDF (1/157 Pages) Dallas Semiconductor – T1 Dual Framer LIU

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GENERAL DESCRIPTION
The DS2196 T1 dual framer LIU is designed for T1
transmission equipment. The DS2196 combines dual
optimized framers together with a LIU. This
combination allows the users to extract and insert
facility data-link (FDL) messages in the receive and
transmit paths, collect line performance data, and
perform basic channel conditioning and maintenance.
The DS2196 contains all of the necessary functions
for connection to T1 lines whether they are DS1 long
haul or DSX–1 short haul. The clock recovery
circuitry automatically adjusts to T1 lines from 0ft to
over 6000ft in length. The device can generate both
DSX–1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths.
The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms.
The device contains a set of internal registers that the
user can access and use to control the unit’s operation
of the unit. Quick access through the parallel control
port allows a single controller to handle many T1
lines. The device fully meets all of the latest T1
specifications.
PACKAGE OUTLINE
DS2196
100
1
DS2196
T1 Dual Framer LIU
FEATURES
§ Two full-featured framers and a short/long-haul
line interface unit (LIU) in one small package
§ Based on Dallas Semiconductor’s single -chip
transceiver (SCT) family
§ Two HDLC controllers with 64-byte buffers that
can be used for the FDL or DS0 channels
§ Supports NPRMs and SPRMs as per ANSI
T1.403-1998
§ Can be combined with a short/long-haul LIU or a
HDSL modem chipset to create a low-cost office
repeater/NIU/CSU, or a HDSL1/HDSL2 terminal
unit with enhanced monitoring and data link
control
§ Supports fractional T1
§ Can convert from D4 to ESF framing and ESF to
D4 framing
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Can generate and detect repeating in-band
patterns from 1 to 8 bits or 16 bits in length
§ Detects and generates RAI-CI and AIS-CI
§ Generates DS1 idle codes
§ On-chip programmable BERT generator and
detector
§ All key signals are routed to pins to support
numerous hardware configurations
§ Supports both NRZ and bipolar interfaces
§ Can create errors in the F-bit position and BERT
interface data paths
§ 8-bit parallel control port that can be used
directly on either multiplexed or nonmultiplexed
buses (Intel or Motorola)
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V supply with 5V tolerant inputs and outputs
§ 100-pin LQFP (14 mm x 14 mm) package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS2196L
DS2196LN
0ºC to +70ºC 100 LQFP
-40ºC to +85ºC 100 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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