S6E1B3 Datasheet, PDF (94/115 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

PRELIMINARY
S6E1B3 Series
11.5 12-bit A/D Converter
Electrical Characteristics of A/D Converter (Preliminary Values)
(VCC=AVCC=1.65 V to 3.6 V, VSS=AVSS=0 V, TA=- 40°C to +105°C)
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
Conversion time *¹
Sampling time *²
Compare clock cycle *³
State transition time to
operation permission
Analog input capacity
Analog input resistance
Interchannel disparity
Analog port input leak current
Symbol
-
-
-
VZT
VFST
-
tS
tCCK
tSTT
CAIN
RAIN
-
-
Pin Name
-
-
-
ANxx
ANxx
-
-
-
-
-
-
-
ANxx
Min
-
- 4.5
- 2.5
- 15
AVRH - 15
2.0
4.0
10
0.6
1.2
3.0
100
200
500
-
-
-
-
-
Value
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
12
4.5
+ 2.5
+ 15
AVRH + 15
-
-
-
10
1000
-
1.0
-
9.7
2.2
-
5.5
10.5
-
4
-
5
Unit
Remarks
bit
LSB
LSB
mV
mV
AVCC ≥ 2.7 V
μs 1.8 ≤ AVCC < 2.7 V
1.65 ≤ AVCC < 1.8 V
AVCC ≥ 2.7 V
μs 1.8 ≤ AVCC < 2.7 V
1.65 ≤ AVCC < 1.8 V
AVCC ≥ 2.7 V
ns 1.8 ≤ AVCC < 2.7 V
1.65 ≤ AVCC < 1.8 V
μs
pF
AVCC ≥ 2.7 V
kΩ 1.8 ≤ AV_CC < 2.7 V
1.65 ≤ AVCC < 1.8 V
LSB
μA
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
Reference voltage
-
AVRH
2.7
-
AVCC
AVCC
V
AVCC ≥ 2.7V
AVCC < 2.7V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The minimum conversion time is computed according to the following conditions:
AVCC ≥ 2.7 V
sampling time=0.6 μs, compare time=1.4 μs
1.8 ≤ AVCC < 2.7 V sampling time=1.2 μs, compare time=2.8 μs
1.65 ≤ AVCC < 1.8 V sampling time=3.0 μs, compare time=7.0 μs
Ensure that the conversion time satisfies the specifications of the sampling time (tS) and compare clock cycle (tCCK).
For details of the settings of the sampling time and compare clock cycle, refer to "Chapter: A/D Converter" in "FM0+ Family
Peripheral Manual Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: The required sampling time varies according to the external impedance.
Set a sampling time that satisfies (Equation 1).
*3: The compare time (tC) is the result of (Equation 2).
Document Number: 001-99224 Rev.**
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