S6E1B3 Datasheet, PDF (1/115 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller

PRELIMINARY
S6E1B3 Series
32-bit ARM^® Cortex^®-M0+
FM0+ Microcontroller
The S6E1B3 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power
consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of
peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I²C, I²S, Smart Card, and USB).
The products which are described in this data sheet are placed into TYPE2-M0+ product categories in "FM0+ Family Peripheral
Manual".
Features
32-bit ARM Cortex-M0+ Core
Processor version: r0p1
Maximum operating frequency: 40.8 MHz
Nested Vectored Interrupt Controller (NVIC): 1 NMI
(non-maskable interrupt) and 24 peripheral interrupt with 4
selectable interrupt priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
Bit Band Operation
Compatible with Cortex-M3 bit band operation.
On-Chip Memory
Flash memory
 Up to 512 K+48 Kbytes
 Dual bank
 upper bank : 512 Kbytes(64 Kbytes x 8)
• lower bank : 48 Kbytes(8K bytes x 6)
 Read cycle: 0 wait-cycle
 Security function for code protection
 SRAM
The on-chip SRAM of this series has one independent SRAM .
 Up to SRAM: 60 K+4 Kbytes
 4Kbytes: can retain value in Deep standby Mode
USB Interface
USB interface is composed of Device and Host
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
USB Device
 USB 2.0 Full-Speed supported
 Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
• EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
• EndPoint 1 to 5 comprise Double Buffer
• The size of each EndPoint is according to the follows
• EndPoint 0, 2 to 5 : 64 bytes
• EndPoint 1 : 256 bytes
USB host
 USB 2.0 Full/Low-Speed supported
 Bulk-transfer, Interrupt-transfer and Isochronous-transfer
support
 USB Device connected/disconnected automatically detect
 IN/OUT token handshake packet automatically
 Max 256-byte packet-length supported
 Wake-up function supported
Multi-Function Serial Interface (Max 8channels)
128 bytes with Tx/Rx FIFO in all channels (The number of
FIFO steps varies depending on the settings of the
communication mode or bit length.)
The operation mode of each channel can be selected from
one of the following.
 UART
 CSIO (CSIO is known to many customers as SPI)
 I²C
 UART
 Full duplex double buffer
 Parity can be enabled or disabled.
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Various error detection functions (parity errors, framing
errors, and overrun errors)
CSIO (also known as SPI)
 Full duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detection function
 Serial chip select function (ch1 and ch3 only)
 Data length: 5 to 16 bits
 I²C
 Standard-mode (Max: 100 kbps) supported / Fast-mode
(Max 400 kbps) supported.
 I²S
 Using CSIO (ch.5, ch.6) and I²S clock generator
 Supports two transfer protocol
• I²S
• MSB-justified
 Master mode only
Cypress Semiconductor Corporation
Document Number: 001-99224 Rev.**
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised August 31, 2015