W134M_05 Datasheet, PDF (9/12 Pages) Cypress Semiconductor – Direct Rambus™ Clock Generator

Device Characteristics
Parameter
t_CYCLE
t_J
t_STEP
t_ERR,PD
t_ERR,SSC
V_X,STOP
V_X
V_COS
V_OH
V_OL
r_OUT
I_OZ
I_OZ,STOP
DC
t_DC,ERR
t_R,t_F
t_CR,CF
Description
Clock Cycle Time
Cycle-to-Cycle Jitter at Clk/ClkB^[9]
Total Jitter over 2, 3, or 4 Clock Cycles^[9]
266-MHz Cycle-to-Cycle Jitter^[10]
266-MHz Total Jitter over 2, 3, or 4 Clock Cycles^[10]
Phase Aligner Phase Step Size (at Clk/ClkB)
Phase Detector Phase Error for Distributed Loop Measured at
PclkM-SynclkN (rising edges) (does not include clock jitter)
PLL Output Phase Error when Tracking SSC
Output Voltage during Clk Stop (StopB=0)
Differential Output Crossing-Point Voltage
Output Voltage Swing (p-p single-ended)^[11]
Output High Voltage
Output Low voltage
Output Dynamic Resistance (at pins)^[12]
Output Current during Hi-Z (S0 = 0, S1 = 1)
Output Current during Clk Stop (StopB = 0)
Output Duty Cycle over 10,000 Cycles
Output Cycle-to-Cycle Duty Cycle Error
Output Rise and Fall Times (measured at 20%–80% of output voltage)
Difference between Output Rise and Fall Times on the Same Pin of a
Single Device (20%–80%)
Notes:
9. Output Jitter spec measured at t_CYCLE = 2.5 ns.
10. Output Jitter Spec measured at t_CYCLE = 3.75 ns.
11. V_COS = V_OH–V_OL.
12. r_OUT = DV_O/ D I_O. This is defined at the output pins.
W134M/W134S
Min.
2.5
–
–
–
–
1
–100
–100
1.1
1.3
0.4
–
1.0
12
–
–
40
–
250
–
Max.
3.75
60
100
100
160
–
100
100
2.0
1.8
0.6
2.0
–
50
50
500
60
50
500
100
Unit
ns
ps
ps
ps
ps
ps
ps
ps
V
V
V
V
V
Ω
µA
µA
%t_CYCLE
ps
ps
ps
Document #: 38-07426 Rev. *C
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