W134M_05 Datasheet, PDF (2/12 Pages) Cypress Semiconductor – Direct Rambus™ Clock Generator

W134M/W134S
Pin Definitions
Pin Name
REFCLK
PCLKM
SYNCLKN
STOPB
PWRDNB
MULT 0:1
No.
2
6
7
11
12
15, 14
Type
Description
I Reference Clock Input. Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
I Phase Detector Input. The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
I Phase Detector Input. The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
I Clock Output Enable. When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
I Active LOW Power-down. When this input is driven to active LOW, it disables the differ-
ential Rambus Channel clocks and places the W134M/W134S in power-down mode.
I PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
MULT0
0
0
1
1
MULT1
0
1
1
0
W134M
PLL/REFCLK
4.5
6
8
5.333
W134S
PLL/REFCLK
4
6
8
5.333
CLK, CLKB
S0, S1
20, 18
24, 23
O Complementary Output Clock. Differential Rambus Channel clock outputs.
I Mode Control Input. These inputs control the operating mode of the W134M/W134S.
S0
S1
MODE
0
0
Normal
0
1
Output Enable Test
1
0
Bypass
1
1
Test
NC
VDDIR
VDDIPD
VDD
GND
19
– No Connect
1
RefV Reference for REFCLK. Voltage reference for input reference clock.
10
RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.
3, 9, 16, 22
P Power Connection. Power supply for core logic and output buffers. Connected to 3.3V
supply.
4, 5, 8, 13, 17, G Ground Connection. Connect all ground pins to the common system ground plane.
21
W133
W158
W159
W161
W167
CY2210
Refclk
W134M/W134S
PLL ^Phase
Align
D
Busclk
RMC
RAC
MN
4
DLL
Pclk
Synclk
Gear
Ratio
Logic
Figure 1. DDLL System Architecture
Document #: 38-07426 Rev. *C
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