W134M_05 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – Direct Rambus™ Clock Generator

Timing Diagrams
Power-down Exit and Entry
PwrDnB
Clk/ClkB
Output Enable Control
StopB
Clk/ClkB
t_POWERUP
t_ON
t_CLKON
t_CLKSETL
W134M/W134S
t_POWERDN
t_STOP
t_CLKOFF
Mult0 and/or Mult1
Output clock
not specified
glitches may
Clock enabled
and glitch-free
occur
Clock output settled within
50 ps of the phase before
disabled
Figure 5. State Transition Timing Diagrams
t_MULT
Clk/ClkB
Figure 6. Multiply Transition Timing
Table 8. State Transition Latency Specifications
Transition
A
C
K
G
H
M
J
From
Power-down
Power-down
Power-down
V_DD ON
V_DD ON
V_DD ON
Normal
To
Normal
Clk Stop
Test
Normal
Clk Stop
Test
Normal
Transition Latency
Parameter Max.
Description
t_POWERUP
t_POWERUP
3 ms
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding t_DISTLOCK).
Time from PwrDnB until the internal PLL and clock has
turned ON and settled.
t_POWERUP
t_POWERUP
t_POWERUP
3 ms
3 ms
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding t_DISTLOCK).
Time from V_DD is applied and settled until Clk/ClkB
output settled (excluding t_DISTLOCK).
Time from V_DD is applied and settled until internal PLL
and clock has turned ON and settled.
t_POWERUP 3 ms Time from V_DD is applied and settled until internal PLL
and clock has turned ON and settled.
t_MULT
1 ms Time from when Mult0 or Mult1 changed until Clk/ClkB
output resettled (excluding t_DISTLOCK).
Document #: 38-07426 Rev. *C
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