CYD02S36V_11 Datasheet, PDF (9/28 Pages) Cypress Semiconductor – FLEx36™ 3.3 V (64K x 36) Synchronous Dual-Port RAM

CYD02S36V/36VA
Figure 2. Counter, Mask, and Mirror Logic Block Diagram^[1]
CNT/MSK
CNTEN
ADS
CNTRST
MRST
Decode
Logic
Bidirectional
Address
Lines
CLK
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
From
16
Load / Increment
Address
Lines
Mirror
1
0
From
16
Mask
Increment
Register
Logic _Wrap
1 ^Counter
0
To Readback
and Address
Decode
16
From
16
Mask
From
16
+1
Counter
+2
16
Bit 0
1
0
1
0
Wrap
Detect
16
Wrap
To
Counter
Document Number: 38-06076 Rev. *J
Page 9 of 28
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