CYD02S36V_11 Datasheet, PDF (10/28 Pages) Cypress Semiconductor – FLEx36™ 3.3 V (64K x 36) Synchronous Dual-Port RAM

CYD02S36V/36VA
Figure 3. Programmable Counter-Mask Register Operation^[17]
Example:
CNTINT
Load
Counter-Mask
Register = 3F
H
00
0s
011 1 11 1
2¹⁵ 2¹⁴
2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰
Masked Address
Unmasked Address
Load
Address
Counter = 8
H
XX
2¹⁵ 2¹⁴
Xs
X0 0 1 0 0 0
2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰
Max
Address
Register
Max + 1
Address
Register
L
XX
2¹⁵ 2¹⁴
H
XX
2¹⁵ 2¹⁴
Xs
X1 1 1 1 1 1
2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰
Xs
X0 0 1 0 0 0
2⁶ 2⁵ 2⁴ 2³ 2² 2¹ 2⁰
Mask
Register
bit-0
Address
Counter
bit-0
IEEE 1149.1 Serial Boundary Scan (JTAG)^[18]
The FLEx36 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V IO logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V_DD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester must be configured to never enter the PAUSE-DR state.
Table 4. Identification Register Definitions
Instruction Field
Revision number (31:28)
Cypress device ID (27:12)
Cypress JEDEC ID (11:1)
ID register presence (0)
Value
0h
C001h
034h
1
Description
Reserved for version number.
Defines Cypress part number for CYD02S36V/36VA
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Notes
17. The “X” in this diagram represents the counter upper bits.
18. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document Number: 38-06076 Rev. *J
Page 10 of 28
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