CYD02S36V_11 Datasheet, PDF (2/28 Pages) Cypress Semiconductor – FLEx36™ 3.3 V (64K x 36) Synchronous Dual-Port RAM

Logic Block Diagram
FTSEL_L
PORTSTD[1:0]_L
DQ [35:0]_L
BE [3:0]_L
CE0_L
CE1_L
OE_L
R/W_L
CONFIG Block
IO
Control
CYD02S36V/36VA
CONFIG Block
IO
Control
FTSEL_R
PORTSTD[1:0]_R
DQ [35:0]_R
BE [3:0]_R
CCEE01_RR
OE_R
R/W_R
Dual Ported Array
A [15:0]_L
CNATD/MS_LSK_L
CNTEN_L
CNTRST_L
RET_L
CNTINT_L
C_L
WRP_L
INT_L
BUSY_L
Arbitration Logic
BUSY_R
Address &
Counter Logic
Address &
Counter Logic
Mailboxes
INT_R
READY_L
LowSPD_L
JTAG
RESET
LOGIC
A [15:0]_R
CNCATND/TMSES_RNKRR
CNTRST_R
RET_R
CNCTI_RNT_R
WRP_R
TRST
TMS
TDI
TDO
TCK
MRST
READY_R
LowSPD_R
Document Number: 38-06076 Rev. *J
Page 2 of 28
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