CY8C36 Datasheet, PDF (9/99 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®3: CY8C36 Family Data Sheet
Figure 2-5 and Figure 2-6 show an example schematic and an
example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
„ The two pins labeled Vddd must be connected together.
Figure 2-5 and Power System on page 25. The trace between
the two Vccd pins should be as short as possible.
„ The two pins labeled Vssd must be connected together.
„ The two pins labeled Vccd must be connected together, and
have capacitors connected between them as shown in
Figure 2-5. Example Schematic for 100-Pin TQFP Part with Power Connections
Vddd
Vddd
Vccd
Vddd
C1
C2
C3
1uF
0.1uF
0.1uF
C6
0.1uF
Vssd
Vssd
Vssd Vssd
U2
CY8C55xx
Vssd
1
2
3
4
5
6
7
8
9
10
Vddd
11
12
13
Vssd 14
15
16
17
18
19
20
21
22
23
24
25
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
Vddio0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0out, P0[1]
OA2out, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
kHzXin, P15[3]
kHzXout, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3out, P3[7]
OA1out, P3[6]
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vddd
Vdda
C8
C13
0.1uF
1uF
Vssd
Vssd
Vdda
Vssa
Vcca
Vssd
C9
1uF
Vssa
Vdda
C10
0.1uF
Vssa
Vddd
C12
0.1uF
Vssd
C16
C15
0.1uF
1uF
Vssd
Vddd
C11
0.1uF
Vssd
Document Number: 001-53413 Rev. *B
Page 9 of 99
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