CY14B101L_09 Datasheet, PDF (9/18 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) nvSRAM

CY14B101L
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Parameter
Alt
Description
25 ns
Min Max
35 ns
Min Max
t_ACE
t_RC ^[7]
t_AA ^[8]
t_DOE
t_OHA ^[8]
t_LZCE ^[9]
t_HZCE ^[9]
t_LZOE ^[9]
t_HZOE ^[9]
t_PU ^[6]
t_PD ^[6]
t_ELQV
t_AVAV, t_ELEH
t_AVQV
t_GLQV
t_AXQX
t_ELQX
t_EHQZ
t_GLQX
t_GHQZ
t_ELICCH
t_EHICCL
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25
35
25
35
25
35
12
15
3
3
3
3
10
13
0
0
10
13
0
0
25
35
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled ^{[7, 8, 10]}
45 ns
Unit
Min Max
45 ns
45
ns
45 ns
20 ns
3
ns
3
ns
15 ns
0
ns
15 ns
0
ns
45 ns
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Figure 6. SRAM Read Cycle 2: CE and OE Controlled ^{[7, 10]}
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Notes
7. WE and HSB must be HIGH during SRAM READ cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
10. HSB must remain high during READ and WRITE cycles.
Document Number: 001-06400 Rev. *J
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Page 9 of 18
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