CY14B101L_09 Datasheet, PDF (11/18 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) nvSRAM

CY14B101L
AutoStore or Power Up RECALL
Parameter
t_HRECALL ^[13]
t_STORE ^{[14, 15]}
V_SWITCH
t_VCCRISE
Alt
t_RESTORE
t_HLHZ
Description
Power up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
V_CC Rise Time
CY14B101L
Unit
Min
Max
20
ms
12.5
ms
2.65
V
150
μs
Switching Waveforms
Figure 9. AutoStore/Power Up RECALL
V_CC
V_SWITCH
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
tVCCRISE
AutoStore
tSTORE
POWER-UP RECALL
Read & Write Inhibited
tHRECALL
tHRECALL
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below V_SWITCH
tSTORE
Notes
13. t_HRECALL starts from the time V_CC rises above V_SWITCH.
14. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
15. Industrial Grade devices requires 15 ms max.
Document Number: 001-06400 Rev. *J
Page 11 of 18
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